The invention relates to the measurement of the thickness of an interlevel dielectric within semiconductor chips. Specifically, the invention involves a method and apparatus for accurately measuring the interlevel dielectric thickness, after chemical-mechanical planarization, above a plurality of structures within a complex semiconductor chip, such as a non-volatile memory chip.
In the fabrication of semiconductor chips today, it is important that insulating layers have a smooth surface topography. For example, having a smooth surface topography provides increased resolution and relieves depth of focus constraints in photolithography. Planarized surfaces on dielectric layers are often obtained using a process known as chemical-mechanical planarization (CMP). This process planarizes a dielectric layer formed, for example, over gate structures in a semiconductor chip thus facilitating easier fabrication.
In addition to controlling the smoothness or degree of planarization of the dielectric layer, it is often imperative that the thickness of an interlevel dielectric formed over gate structures also be strictly controlled. The thickness of the dielectric layer above chip components such as gate structures can have a direct effect on performance, especially in multi-level chips. If the dielectric layer, after chemical-mechanical planarization, is too thin, the electrical characteristic of the underlying structures is altered. If the layer is too thick, it will adversely affect the successful performance of subsequent process steps, such as contact hole etching. Also, the tolerances defining acceptable dielectric layer thicknesses are often very strict.
One technique for measuring post-chemical-mechanical planarization thickness of an interlevel dielectric appears to provide acceptable results when used with relatively simple semiconductor chips. Such chips tend to comprise either only one type of structure or multiple, but very similar, types of structures. Typically, a monitor box is formed directly on the chip at the same time and by the same process as the other structures on the chip. Thus, the monitor box represents a structure of the type used in the chip in both height and material constitution. The monitor box provides a location on which measurements of the thickness of a subsequently formed and planarized dielectric layer can be made.